EMC is a critical part of product development for any company that wants to take a product to market. Many EMC design guidelines simply parrot incorrect or poorly contextualized information found online or in IC application notes. Some of these guidelines were valid in the 1980s, but they may not be universally valid today except in some corner cases that are no longer mainstream. Designers should understand which EMC design guidelines to avoid to ensure they comply with emissions regulations.
This is easier said than done. A lot of bad design advice can be found in IC application notes, and it’s easy to assume the IC companies are doing everything correctly. However, IC manufacturers are not circuit board design experts and they are not required to perform full emissions testing with their products. In addition, EMC design guidelines found online are often a contradictory amalgamation of application note guidelines and outdated advice from so-called “experts” who aren’t board designers. Before you start following EMC design guidelines from the 1980s, read our list of design advice to avoid so you can build boards correctly.
Here are the major EMI design myths you’ll find online and discussed below:
- 90 Degree Angles Create EMI
- Place Guard Rails Along Clock Traces
- Following the 3W Rule Prevents EMI
- Differential Pairs Are Immune to EMI
- Ferrite Beads Solve All Your EMI Problems
- All Corners Are Strong Radiators
Some Major EMC Design Myths
Some of the most misunderstood points around EMC design for PCBs relate to the most fundamental electrical aspects of board design: stack-up construction and grounding. Generally, the design guidelines you see from “experts” or application notes totally omit these points and they focus on routing or component placement. Professional EMC engineers take a holistic view of the board as they are complex systems, and I hope the following list of design guidelines summarizes the right way to think about EMC design in your next product.
Myth 1: 90 Degree Angles Create EMI
The 45 vs. 90 degree angle thing is mythical and is often taken wildly out of context. The 45 vs. 90 degree angle myth only becomes reality well above 100 GHz, but even then it will not cause you to fail an EMC test unless you fail to design the stack-up correctly. There have been many studies that have looked into the potential board failures that can result from 90 degree routing, which I’ve compiled in an earlier article. One recent objection I saw was a mention of some mysterious capacitance that gets created by the 90 degree bend, which would then create an impedance discontinuity and reflections, although this has nothing to do with failing an emissions test. The 90-degree routing guidelines are often mis-applied to EMC design with the assumption that the stack-up is also mis-constructed, a generalization which may not be true.
Another objection states that current becomes concentrated along the corner in 90-degree bend, which would generate more EMI. While the current density is higher along the corner regions in a trace, the idea that this will greatly increase EMI is false. Inductively coupled EMI depends on the magnetic flux, which depends on the total current, not on current density. The total current being routed along a 90-degree bend does not increase or decrease, so in the near-field limit, you will not see an increase in EMI. The exception here is when you are in a resonating limit, where the corner region becomes a resonator at very high frequencies and emits coherent radiation. In this case, the apparent emitted power is larger due to superposition, as you would expect with any leaky cavity resonator.
Myth 2: Place Guard Rails Along Clock Traces
I’ve seen guidelines mentioning placement of guard rails around clock traces. These guidelines are typically applied to system clocks, where a single clock is routed throughout the entire system while maintaining very precise phase throughout the system. No one does this in modern designs for two reasons:
- Guard traces are known to make crosstalk problems worse, a fact which has been demonstrated by prominent EMC experts in the industry.
- Modern digital protocols use source-synchronous clocking (e.g., SPI, I2C, DDR), embedded clocking (PCIe, Ethernet), or no clocking at all (UART).
If we suppose you were using an external reference clock that requires some isolation, why would a designer not just use copper pour? Copper needs to be etched to form the clock trace regardless, so some copper can be left behind unless there is some manufacturability objection, such as warping in a large board. In addition, you certainly wouldn’t want to triple your net count when routing a protocol with an embedded clock by placing guard traces around the clock.
Myth 3: Following the 3W Rule Prevents EMI
Most designers will tell you to use a trace-to-trace spacing of 3W when routing your design, which is the typical crosstalk prevention rule of thumb from 20 years ago. I’ve heard numbers ranging from 5W to 1W. While providing spacing between traces is important for preventing crosstalk, what’s more important is placing a reference plane near traces for preventing radiated EMI. This applies in all-digital systems and mixed-signal systems, both of which should use reference plane layers and should not have traces routed over regions with reference conductor discontinuities or a complete absence of a reference conductor.
For impedance controlled systems, the proper way to provide isolation is to use ground pour in a coplanar arrangement in addition to placing a reference layer in the PCB stack-up. Generally, the procedure is to look at how nearby conductors modify the impedance of the trace by comparing the impedance of a trace without ground to a coplanar trace in the same stack-up and layer. If you bring the ground pour too close, you now have distributed parasitic capacitance in parallel with the line’s distributed self-capacitance, so the impedance will decrease.
Basic method of moments (MoM)/boundary element field solvers that are found in Cadence, Altium, Polar, Mentor, and probably some other stack-up calculators can be used to perform this comparison. I actually did this investigation with an MoM field solver and I’m presenting the results as part of my upcoming presentation at PCB West 2021. You can get as close as 0.5W or less, depending on the layer thickness to trace width ratio and the dielectric constant of the laminate material. If you really want to kick it into high gear, you would use a field solver and you would calculate shielding effectiveness vs. trace-to-copper separation, which is something that can be directly compared in two simulations with the client’s products and is specific to EMC design beyond impedance controlled routing.
Myth 4: Differential Pairs Are Immune to EMI
In differential pairs, everyone focuses on reduction of common mode noise, which is the major advantage of differential pair routing. However, differential pairs also create EMI that can be received by other differential pairs as differential mode crosstalk. I’ve discussed this in detail in an earlier article on Altium’s PCB design blog; I encourage readers to understand the field strength argument here and how the strength of crosstalk relates to the PCB stack-up and distance to a nearby reference plane.
Some EMC guidelines will then state that differential pairs should be placed as close as possible, but without a clear explanation as to why or what the design goal is. I assume this would target differential crosstalk as the in-plane inductance would be smaller, but very few EMC design guidelines ever mention differential crosstalk or radiated differential mode noise. In reality, you cannot just place pairs closer to each other without violating impedance tolerances. This is critical in differential pair design as differential pairs are prominently used in high speed PCB routing. You can’t just start putting pairs closer because the differential impedance of the pair is very sensitive to the spacing between the two traces, and you might not hit your impedance goals.
I’ve read reports of designers violating the impedance target in newer PCIe generations, but I’ve never tested it. Always make sure you test your channel design if you plan to violate an impedance target from your signaling specification. You would need to design a standard test channel (such as IEEE P370) with a standard test fixture and take 4-port S-parameter measurements to evaluate the channel. This is the standard approach to dealing with differential pairs, you don’t just shove them closer together unless you can verify the channel will meet signal integrity targets.
Myth 5: Ferrite Beads Solve All Your EMI Problems
Ferrite beads are intended to target very specific problems in power systems involving low-frequency to mid-frequency noise, as I’ve discussed in a recent article. Noise from EMI can be spread over a broad bandwidth, and an entire noise spectrum can’t be targeted with ferrite beads alone. The typical approach is to implement a grounding strategy, add filtering circuits, and then use ferrites as needed to target specific noise sources, particularly in power systems. Enclosure grounding in a design and shielding materials as a last resort may also be needed to ensure EMC tests can be passed, particularly when a product might be deployed in a noisy environment or when it could be prone to ESD. This is how SI/PI engineers approach EMC.
Myth 6: All Corners Are Strong Radiators
One guideline that is misunderstood as an EMI prevention measure is long, straight routing is preferred. This is valid because, in high-speed/high-frequency designs, longer traces experience more losses, and you would like to avoid losses to ensure signals can be recovered at the receiver. This is sometimes discussed as an EMI generation problem, which is incorrect. Longer traces do not act like radiating antennas at lower frequencies except in a particular case where you have a closed (impedance mismatched) cavity, creating a resonating cavity that emits strongly at specific frequencies.
It is true that, in general, traces emit some radiation, even when the interconnect is impedance matched at both ends and there are no reflections. However, the amount of radiation is so minor as to be negligible as long as the traces are placed close to a reference plane. As a result, things like routing longer traces or routing around a bend will not cause your design to fail EMC testing as long as the stack-up is designed correctly. It only becomes non-negligible when designers don’t create a proper reference plane or route over a gap in a reference plane, but this is a general guideline that applies far beyond routing around bends and corners. Again, this a stack-up design problem and not a routing problem.
Any traces carrying a time-varying signal are always antennas, the amount of radiation they produce depends on the proximity to the image emitter that is induced in the reference plane. This means if you place the reference plane closer to the trace, you’ll have less radiation. This is one reason HDI designs don’t have the same EMI problems as, say, a two-layer digital design. The two-layer design will have massive parasitic inductance in its interconnects by comparison, and EMI is especially bad when these simple designs don’t use a ground plane or ground pour to provide return paths. Once you get into the 100 GHz range you may have problems, in which case you’re now dealing with a wave propagation problem that can be analyzed by treating the corner regions as resonating cavities.
Summary
In the end, EMC design guidelines related to routing are actually related to stack-up design and grounding. Most routing EMC failures that masquerade as a routing problem are eliminated when you design the stack-up correctly. In other cases, even if the design is created correctly, simple things like changing reference planes with clock or signal traces can create enough EMI to cause an EMC testing failure. Simple solutions like changing the layer arrangement or adding grounded vias along layer transitions are enough to ensure a consistent reference is enforced throughout the board, giving you a strong foundation to ensure EMC.
Don’t rely on outdated EMC design guidelines to build your advanced electronics. If your company is pushing the limits of new technology, it pays to work with an experienced PCB design firm that understands the context behind EMC myths and how to design electronics with the right physical layout to prevent EMI problems. PCBLOOP helps consumer OEMs, industrial primes, and private companies in multiple industries design modern PCBs and create cutting-edge embedded technology. We’ve also partnered directly with EDA companies and advanced ITAR-compliant PCB manufacturers, and we’ll make sure your next high speed digital system is fully manufacturable at scale. Contact PCBLOOP for a consultation.
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